Boost Converter Design and Simulation

Background

    Previously I published a post detailing the design and simulation of a switched mode power supply that stepped down voltage. That step down regulator is known as a buck converter but now it is time to design and simulate the opposite behavior which is stepping up an input voltage. Or as it's known: boosting the output voltage. Just like its buck counterpart, there are a lot of commercial products out there already, but the fun is always in the design (at least for me). 

    Today I will be documenting the design and simulation of the power stage in a step up switched mode power supply, also known as a boost converter. 


Specifications

Let's get to the specifications. Just like the buck converter we have the same specification values expect that this time the output voltage will be greater than the input voltage. 

Here are the specifications chosen for this design: 


Setup

Here is the circuit topology for a typical boost converter. It uses the same general components as the buck converter, the only difference is the placement. As you can see, I am using the same Schottky diode but a different transistor. This time it's an NMOS. 


Calculations

The calculations for the boost converter are very similar to the buck converter. Here I will just number crunch so I can focus on the output waveforms. 

Determining value of D

For the boost converter the duty cycle ratio D can be calculated with EQ. 1 below:
EQ. 1

The diode voltage drop is still the same since I used the same part again. Vd = 0.55 Input voltage Vin=9V and output Voltage Vout=18V just to change it up a bit. Now to just plug in these values in to EQ. 1 to get D.

Inductance
The inductance is calculated using EQ. 2 below. The difference is that here the inductance only relies on Vin rather than Vd and Vout as seen on the buck converter.
EQ. 2

Once again, ton is calculated the same way. It's just the time the square wave spends on HIGH. Now we can just plug in our known values to solve for inductance:


Filter capacitance
To calculate the filter capacitance we use EQ. 3: 
EQ. 3
Iout is 500mA, toff is basically the time the time the square wave will spend in the LOW state. This can be calculated just by subtracting the time spent high from the total period which is 10 microseconds. Here the voltage ripple was chosen to be 500mV. Now that all values are known, we can plug them in.



Choosing load resistance
To simulate the load at its maximum capacitance and verify proper operation it is important to choose an appropriate value for the load resistor. Just by using Ohm's law, it can be determined as follows:





MOSFET driver voltage
Next we need to calculate the switching voltage levels for our driver square wave. The chosen N-type MOSFET for this application is the IRF520 which has a gate-source threshold voltage of 2.0V to 4.0V. The tested threshold voltage was Vto = 3.59V. To ensure operation in triode region, the peak of the square wave will be set to 10V for HIGH and 0V for LOW.



Simulation
Now that all component values are calculated it's time to fill them in on the circuit. 


Output Waveform
This time I set the end time to 8ms to verify it stabilized but cropped it at 5.0ms just to get a clearer image. Once again, it stabilizes at the intended output, here its approximately at 18V.



I zoomed in on a stable region and marked the maximum and minimum voltages of the ripple. Here the maximum is 18.056V and the minimum is 17.360V. That's a ripple of .696V which is slightly higher than the specified voltage. 


To calculate efficiency I also needed to measure the input and output currents as seen below. The red waveform is the input current and the blue one is the output current. I placed some markers on the peaks and had 501.5671mA for the output current which was intended to be 500mA. The maximum input current was measured to be 1.0815A which is needed for calculation of the efficiency. 


Efficiency calculation
In switched mode power supplies it's good to look at the efficiency. Normally the efficiency for switched mode power supplies are high, upwards of 80%. To calculate the efficiency I will just use a simplified formula of the ratio of power out and power in as seen below:
where


This gives an efficiency of 92.725% which is very good and why these types of converters are used. 

Output Voltage vs Duty Cycle
I varied the duty cycle and logged the output voltage at each duty cycle to plot it. The plot below shows a non-linear relationship between them. Depending on how much one is willing to round, it could be linear or not, but within this design, the relation wasn't as linear as it was for the buck converter. 


Conclusion
The boost converter design process was very similar to the buck converter. There were minor differences, but the most evident was that the output voltage vs duty cycle doesn't seem to be as linearly related to each other as it was for the buck converter. The efficiency remained very high and a N-type MOSFET was used in this case because the gate voltage needed in the placement was feasible. The voltage and current ripple were slightly higher than I calculated. Next time, I would design with lower ripples if my application is that sensitive to the slight inaccuracy of the ripple. Overall, it was still a good introductory process and very interesting. 






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