RF Filter, Tuned Amplifier and Mixer design and simulation in PSPICE

 Background

A superheterodyne receiver is present in almost all modern radios. This type of radio receiver has different stages that convert a received signal from its original carrier frequency to an intermediate frequency(IF). This conversion process is done through a mixer. The main components can be seen in the block diagram below. Here I will be focusing on the design for the RF filter, RF Tuned amplifier and the mixer.

Overview of Design

In this post I will document the process of designing and simulating three components of a superheterodyne receiver. The RF filter, RF amplifier and the mixer with an oscillator.

• The design is to operate at a resonant frequency of 40kHz
• Tuned amplifier will have a gain of 35V/V and bias current Ic=15mA
• The intermediate frequency of the mixer is to be 9kHz

I will begin with the filter design, then the RF amplifier and finally with the mixer.

RF Filter Design

Specifications of RF Filter

The specifications of the passive filter are as follows:

• Q = 10
• Center frequency fr=40kHz

The general topology of an RF tank circuit can be constructed using a RLC circuit as shown in the figure below:

A transfer function of the above circuit can be extracted by first converting the components to their s-domain properties. 

Next, we can extract the transfer function using nodal analysis by keeping the same ground reference node and labeling Vout as the junction where the components meet:

Now that the transfer function is extracted, we can convert to standard form by multiplying by 1/(CLR) and get EQ. 1:

EQ. 1 Standard form of transfer function

The general transfer function for a bandpass filter is known to be EQ. 2a:

EQ. 2a general transfer function for bandpass filter

Here since the filter is a passive filter, in EQ. 2a, the gain A0=1. This gives us a modified equation EQ. 2b:

EQ. 2b

Now we can solve for the component values by comparing EQ. 1 to EQ. 2b. 

We notice the following relations based on the coefficients of each s term:

Another further observation is that both relations have the same capacitor value C in common. 

To computer this capacitance value, we must get the angular frequency that meets the center frequency specification fr = 40kHz with Q = 10 

Since capacitor values are harder to adjust or to choose from, a standard capacitor value of C = 10nF is chosen. Now that C is known in both equations, we can calculate the resistor value and inductor values as follows:

Simulation

After calculating all values, we can finally set up the following schematic:

Finalized design for RF circuit with fr=40kHz

We can then run a frequency response analysis on PSPICE to get the output waveform below. 

Frequency Response of bandpass filter with 40kHz center frequency and labeled -3dB points

From the waveform labels, we see that in order to get Q=10, the bandwidth must be =4k so we can calculate the corner frequencies to be at: 

Which the frequency response confirms. This circuit can now be added to our amplifier.

Tuned Amplifier Design

Specifications

The specifications for the tuned amplifier are as follows:

• DC bias Ic=15mA
• Voltage gain Av=35V/V

DC bias

For DC bias, we can assume that the LC tank circuit at the collector will act as a perfect short since an inductor in DC is just a short. To facilitate calculations, values for the base resistors are chosen to be equal and of a resistance upwards of 10k Ohms.

• RB1=RB2=20k Ohm

At this configuration, we can run a PSPICE simulation by forcing 150mA through Ic to extract our beta value

This gives us a beta value of 171.

To maximize voltage swing, the base voltage Vb is set to approximately half of the supply voltage.

    Next, we must design for the requirement of the collector current Ic=15mA. We can assume that the base-emitter voltage drop is 0.7V and that the emitter current is approximately equal to the collector current to simplify calculations and allow us to solve for the emitter resistance R_E. 

    Since the tank circuit that will be added will have some resistance in series with the inductor, we have to account for this extra resistance to maintain a quality factor of Q=10. To do so, we will set the emitter resistance R_E to a lower nominal value to help calculations and account for an inductor resistance. Assuming that the resistance of the inductor will be less than 5 Ohms to avoid distortion in the DC bias.

Now that we have the emitter resistance and expected inductor resistance range, we can calculate the base resistors R1 and R2 as follows:

After calculating all needed components, we can set up a schematic and simulate the DC bias in PSpice to verify the needed node voltages.

DC bias of tuned amplifier

Now that the DC bias is set, we can modify the previously calculated values to ensure that our quality factor Q = 10. 

The previously calculated values for our tank circuit were: 

As we can see, the resistance Rold that will be in the tuned amplifier circuit is too high. So we make slight modifications to the RLC values to keep R_tank <100 Ohms. We simply change them by a factor of 100 to make sure that the resistance of the tank circuit is within an allowable range to get the following values of our tank circuit:

To meet the gain requirement of Av=35V/V we must reduce the overall voltage gain. The tank circuit will cause a large gain due to the large impedance at resonance. This impedance can be calculated as follows:

To achieve the gain using this impedance, we can split the emitter resistance R_E into two separate resistors. One to act as an emitter degeneration resistor which will allow us to control the gain more precisely. The gain of the circuit with emitter degeneration becomes:

Simulation

Now that all the values are calculated, we can set up the circuit in the following schematic:

Single tuned amplifier final circuit with gain of 40V/V and fr=40kHz

We can now run a frequency response simulation in PSpice to get the following output waveform:

Frequency response of tuned amplifier with labeled -3dB points and midband gain.

The frequency response plot shows that the midband gain  A_vmid = 35.159V/V

and since Q = 10 we can find the bandwidth:

From midpoint, the -3dB frequency points should be

At each of these frequencies, the gain should be 

which according to the labeled markers, it is very close to the simulation results.

To see the FFT output and the first 5 harmonics, we set the input to be a sine wave with an amplitude of 1V and a frequency of 4kHz:

FFT of tuned amplifier with labeled harmonics

From the plot, we can extract the first 5 harmonics into the following table:

And we can calculate the total harmonic distortion THD by taking the RMS voltage values of each harmonic:

Mixer Design

After verifying functionality of the tuned amplifier with the filter stage, we can now proceed with the mixer. 

Specifications of Mixer

The specifications of the mixer are as follows

• ID3 = 5mA
• Intermediate frequency = 9kHz

DC Bias

To calculate the DC bias for ID3 = 5mA we can first calculate the resistor values R1 and R2.

Next, to meet the current requirement if IC = 5mA then the emitter resistor R_E has to be calculated:

Simulation of Mixer

After all values were calculated, we can design the following schematic and simulate the DC bias using PSpice to verify the intended current of 5mA.

Mixer DC bias with 5mA through bottom BJT

Next, we can input a 10kHz sine wave with an amplitude of 10mV to the LO port and a 1kHz sinewave with an amplitude of 100mV to the RF port as seen below to simulate the transient response:

Mixer with differential voltage probing

The output waveform for a transient analysis with a proper output can be seen below:

Transient response of mixer circuit 

We can also simulate the FFT with a frequency response simulation to get the first five harmonics of the mixer:

FFT of mixer with first five harmonics labeled

The intermediate frequency fi = f_RF - f_lo

which is confirmed by the output waveform of the FFT above.

Conclusion

To design a passive filter there is more freedom in choosing component ratios as the gain isn’t considered which removes a constraint when calculating values. For a tuned amplifier with a desired practical gain, it is harder since not only must the ratio of the LRC tank circuit needs to be considered, but also its resonant resistance. The mixer even in simulation, outputs a very nonideal intermediate frequency of 8.8kHz rather than the ideal 9kHz even with ideal components. Practically, for all these implementations, the series resistance of these components must be considered when designing them, however some considerations were taken in the design process which helped mitigate the effects of non-ideal components and designed with the anticipation of a non-ideal breadboard implementation.